december 2013 thermal characteristics fqa13n50c_f109 n-channel qfet ? mosfet 500 v, 13.5 a, 480 m? description ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0 www.fairchildsemi.com 1 fqa13n50c_f109 n-channel qfet ? mosfet these n-channel enhancement mode power field effect transistors are produced using fairchilds proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficiency switched mode power supplies, active power factor correction, electronic lamp ballasts based on half bridge topology. features ? 13.5 a, 500 v, r ds(on) = 480 m? (max.) @ v gs = 10 v, i d = 6.75 a ? low gate charge (typ. 43 nc) ? low crss (typ. 20 pf) ? 100% avalanche tested absolute maximum ratings t c = 2 5c unless otherwise noted. ? improved dv/dt capability to-3pn g d s g s d
fqa13n50c_f109
+ thermal resistance, junction-to-case, max. 0.58 6 ? +
thermal resistance, junction-to-ambient, max. 40 6 ? symbol parameter fqa13n50c_f109 unit v dss drain-source voltage 500 v i d drain current - continuous (t c = 25c) 13.5 a - continuous (t c = 100c) 8.5 a i dm drain current - pulsed (note 1) 54 a v gss gate-source voltage 30 v e as single pulsed avalanche energy (note 2) 860 mj i ar avalanche current (note 1) 13.5 a e ar repetitive avalanche energy (note 1) 21.8 mj dv/dt peak diode recovery dv/dt (note 3) 4.5 v/ns p d power dissipation (t c = 25c) 218 w - derate above 25c 1.56 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering, 1/8" f rom c ase for 5 seconds. 300 c
package marking and ordering information www.fairchildsemi.com 2 fqa13n50c_f109 n-channel qfet ? mosfet part number top mark package reel size tape width quantity fqa13n50c fqa13n50c_f109 to-3pn n/a n/a 30 units packing method tube electrical characteristics t c = 25c unl ess otherwise noted. symbol parameter test conditions min. typ. max. unit off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 500 -- -- v ? bv dss / ?t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25c -- 0.5 -- v/c i dss zero gate voltage drain current v ds = 500 v, v gs = 0 v -- -- 1 a v ds = 400 v, t c = 125c -- -- 10 a i gssf gate-body leakage current, forward v gs = 30 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -30 v, v ds = 0 v -- -- -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2.0 -- 4.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 6.75 a -- 0.39 0.48 ? g fs forward transconductance v ds = 40 v, i d = 6.75 a -- 15 -- s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 1580 2055 pf c oss output capacitance -- 180 235 pf c rss reverse transfer capacitance -- 20 25 pf switching characteristics t d(on) turn-on delay time v dd = 250 v, i d = 13.5 a, r g = 25 ? (note 4) -- 25 60 ns t r turn-on rise time -- 100 210 ns t d(off) turn-off delay time -- 130 270 ns t f turn-off fall time -- 100 210 ns q g total gate charge v ds = 400 v, i d = 13.5 a, v gs = 10 v (note 4) -- 43 56 nc q gs gate-source charge -- 7.5 -- nc q gd gate-drain charge -- 18.5 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 13 a i sm maximum pulsed drain-source diode forward current -- -- 52 a v sd drain-source diode forward voltage v gs = 0 v, i s = 13.5 a -- -- 1.4 v t rr reverse recovery time v gs = 0 v, i s = 13.5 a, di f / dt = 100 a/ s -- 410 -- ns q rr reverse recovery charge -- 4.5 -- c notes: 1. repetitiv e rating : pulse - width limited by maximum j uncti on temperature . 2. l = 5.6 mh, i as = 13.5 a, v dd = 50 v, r g = 25 ?, starting t j = 25c . 3. i sd 13 .5 a, di/dt 200 a/ s, v dd bv dss, s tarting t j = 25c . 4. essentially independent of operating temperature ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0
www.fairchildsemi.com 3 fqa13n50c_f109 n-channel qfet ? mosfet typical characteristics typical characteristics 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 -1 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s pulse test 25 i dr , reverse drain current [a] v sd , source-drain voltage [v] 0 5 10 15 20 25 30 35 0.5 1.0 1.5 v gs = 20v v gs = 10v note : t j = 25 r ds(on) [? ], drain-source on-resistance i d , drain current [a] figure 5. capacitance characteristics figure 6. gate charge characteristics figure 2. transfer characteristics figure 1. on-region characteristics 10 -1 0 10 1 10 -1 10 0 10 1 v gs top : 15.0 v 10.0 v 8.0 v 7.0 v 6.0 v 5.5 v 5.0 v bottom : : .5 v notes : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] 10 v ds , drain-source voltage [v] 4 2 81 0 10 -1 10 0 10 1 150 o c 25 o c -55 o c not es : 1. v ds = 40v 2. 250 s pulse test i d , drain current [a] 6 v gs , gate-source voltage [v] 10 -1 0 10 1 0 500 1000 1500 2000 2500 3000 c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd notes ; 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] 10 v ds , drain-source voltage [v] 0 0 1 2 03 0 0 4 5 0 0 2 4 6 8 10 12 v ds = 250v v ds = 100v v ds = 400v note : i d = 13.5a v gs , gate-source voltage [v] q g , total gate charge [nc] figure 3. on-resistance variation vs drain current and gate voltage figure 4. body diode forward voltage variation with source current and temperature ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0
www.fairchildsemi.com 4 fqa13n50c_f109 n-channel qfet ? mosfet typical characteristics (continued) z ? jc (t), thermal response [ o c/w] v ds , drain-source voltage [v] figure 9. maximum safe operating area -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = 250 a bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 notes : 1. v gs = 10 v 2. i d = 6.75 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] figure 10. maximum drain current vs case temperature t 1 , s q ua re w ave p u lse d u ra tio n [se c] figure 11. transient thermal response curve for fqa13n50c 10 -5 10 4- 10 3- 10 -2 10 1- 10 0 10 1 10 -2 10 -1 10 0 n otes : 1. z (t) = 0.58 /w m ax. 2. d ut jc y factor, d =t 1 /t 2 3. t jm - t c = p dm * z jc (t) single pulse d=0.5 0.02 0.2 0.05 0.1 0.01 t 1 p dm t 2 10 0 10 1 10 2 10 3 10 -1 10 0 10 1 10 2 100 ms 10 s dc 10 ms 1 ms 100 s operation in this area is limited by r ds( on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse i d , drain current [a] 25 50 75 100 125 150 0 2 4 6 8 10 12 14 i d , drain current [a] t c , case temperature [ ] figure 7. breakdown voltage variation vs temperature figure 8. on-resistance variation vs temperature ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0
figure 12. gate charge test circuit & waveform figure 13. resistive switching test circuit & waveforms figure 14. unclamped inductive switching test circuit & waveforms v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs v ds 10% 90% t d(on) t r t on t off t d(off) t f v dd 10v v ds r l dut r g v gs v gs charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut charge v gs 10v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut e as =li as 2 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 ---- 2 1 -------------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) time 10v dut r g l l i d i d t p v gs v gs i g = const. www.fairchildsemi.com 5 fqa13n50c_f109 n-channel qfet ? mosfet ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0
figure 15. peak diode recovery dv /dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period -------------------------- www.fairchildsemi.com 6 fqa13n50c_f109 n-channel qfet ? mosfet ?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0
?2009 f airchild semiconductor corporation fqa13n50c_f109 rev. c0 www.fairchildsemi.com 7 fqa13n50c_f109 n-channel qfet ? mosfet mechanical dimensions figure 16. to3, 3-lead, plastic, eiaj sc-65 package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tt3p0-003
?2009 fairchild semiconductor corporation fqa13n50c_f109 rev. c0 www.fairchildsemi.com 8 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchilds worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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fqa13n50c_f109 n-channel qfet ? mosfet
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